Integrated circuits (ICs) have seen continuous technological advancement, resulting in chips that increasingly perform more logic operations per unit area and at higher operating speeds. The increased capability of integrated circuits has also created more complexity regarding the relationship of various clock or control signals. For example, in a high-speed environment, it may be required that a second clock signal is delayed a certain amount relative to a first clock signal so that data gated by the first clock signal is in an appropriate state on the triggering edge of the second clock signal.
In complex integrated circuits, there may be multiple functional blocks or modules within the integrated circuit that communicate with each other. It is therefore necessary to synchronize the timing of signal transmission and receipt between modules in order to avoid timing errors. Timing errors can cause one or more components to fail to accurately interpret electronic signals as correct data. Many phenomena (physical conditions, digital logic errors, etc.) can result in timing errors, particularly in systems that operate at high speeds and/or have high data throughput rates. Typically, many IC components contain timing circuitry and logic devoted to minimizing timing errors. However, it is always desirable to minimize the physical chip area and the power consumed by IC components, especially by that which is consumed by functions not directly related to the purpose of the system or component.
Some of the electronic components within an IC must be synchronized with other electronic components in the circuit in order to ensure that both sets of electronic components receive the correct data signals at the right time. Failing to synchronize them can yield unreliable or erroneous results. Thus, the rising and/or falling edges of the clock signals must trigger these electronic components at precisely the right time to synchronize their function. To accomplish this crucial requirement, a significant part of the design process for the IC involves analyzing the clock signal paths and the components in these paths to determine the arrival time of rising and/or falling edges of the clock signals at the various synchronized electronic components.
As an example of the importance of reliable timing, microprocessor circuits use clock pulses to synchronize the operations of the microprocessor. Clock pulses can be asynchronous; that is, not synchronized with respect to the clock pulses of other circuits within a complex chip. As a consequence of asynchronous timing, it is possible for the microprocessor to request the data from another circuit while that circuit is not in a stable state. Such a request can cause the microprocessor to receive erroneous data. Similar types of problems can result with other asynchronous real-time data manipulation circuits.
During the design process, various circuit elements must be considered. These include buffering, component placement, and transistor technology, among others. Without proper timing, large scale integrated circuits will not function properly. The operation of highly complex and densely integrated circuits (chips) is typically orchestrated by a system clock signal. The clock signal may take many forms. Regardless of the form, however, the role of the clock signal is to synchronize operations across the entire chip, ensuring that all portions of the chip work together properly. Furthermore, as a result of the ubiquitous nature of the clock signal, this signal must be distributed to virtually every circuit across the entire chip. Clock signals are thus a critical part of most any integrated circuit design.